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ps3410c-0600 2365 ne hopkins court pullman, wa 99163-5601 tel: 509.334.1000 fax: 509.334.9000 e-mail: sales@aha.com www.aha.com advanced hardware architectures product specification aha3410c starlite tm 25 mbytes/sec simultaneous lossless data compression/decompression coprocessor ic
ps3410c-0600 notes to customers am29k and fusion29k are trademarks of advanced micro devices; i960 and solutions 960 are trademarks of intel corporation; coldfire is a trademark of motorola corporation.
advanced hardware architectures, inc. ps3410c-0600 i table of contents 1.0 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 conventions, notations and definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.0 system configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.0 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 data ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.2 dma mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.3 pad word handling in burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.4 dma request signals and status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.4.1 fifo thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.4.2 request during an end-of-record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.4.3 request status bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.5 data format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.6 odd byte handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.6.1 compression input and pad bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.6.2 compression output and pad bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.6.3 decompression input, pad bytes and error checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.6.4 decompression output and pad bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.7 video interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.7.1 video input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.7.2 video output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.8 compression engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.9 decompression engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.10 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.11 low power mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.12 test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.0 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 system configuration 0, address 0x00 - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2 system configuration 1, address 0x01 - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3 input fifo thresholds, address 0x02 - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.4 output fifo thresholds, address 0x03 - read/write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.5 compression ports status, address 0x04 - read only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.6 decompression ports status, address 0x05 - read only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.7 port control, address 0x06 - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.8 interrupt status/control, address 0x07 - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.9 interrupt mask, address 0x09 - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.10 version, address 0x0a - read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.11 decompression record length, address 0x0c, 0x0d, 0x0e, 0x0f - read/write. . . . . . . . . . . . . . . . . . . . 21 4.12 record length, address 0x10, 0x11, 0x12, 0x13 - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 4.13 compression control, address 0x14 - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.14 compression reserved, address 0x15 - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.15 compression configuration, address 0x16, 0x17 - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 4.16 decompression control, address 0x18 - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.17 decompression reserved, address 0x1a - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.18 decompression configuration, address 0x1c, 0x1d - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
advanced hardware architectures, inc. ii ps3410c-0600 5.0 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2 data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.3 video interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.4 system control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.0 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.0 dc electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9 7.1 operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.2 absolute maximum stress ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.0 ac electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 9.0 package specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 10.0 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10.1 available parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10.2 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 11.0 related publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 11.1 aha technical publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 11.2 other technical publications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 appendix a:additional timing diagrams for dma mode transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
advanced hardware architectures, inc. ps3410c-0600 iii figures figure 1: functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 figure 2: microprocessor port write (procmode[1:0]=?01?). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3: microprocessor port read (procmode[1:0]=?01?) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 4: microprocessor port write (procmode[1:0]=?11?). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 5: microprocessor port read (procmode[1:0]=?11?) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 6: dma mode timing for single word writes, strobe condition of dsc=100 . . . . . . . . . . . . . . . . . . . . . . . 7 figure 7: dma mode timing for single word reads, strobe condition of dsc=100 . . . . . . . . . . . . . . . . . . . . . . . 7 figure 8: dma mode timing for four word burst write, one wait state, strobe condition of dsc=100. . . . . . . . 7 figure 9: dma mode timing for four word burst read, one wait state, strobe condition of dsc=100 . . . . . . . 8 figure 10: dma mode timing for eight word burst write, zero wait state, strobe condition of dsc=100 . . . . . . . 8 figure 11: dma mode timing for eight word burst read, zero wait state, strobe condition of dsc=100 . . . . . . . 8 figure 12: fifo threshold example (ift=4, dsc=2, 1 word already in fifo) . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 13: request vs. end-of-record, strobe condition of dsc=010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 14: timing diagram, video input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 15: timing diagram, video output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 16: pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 17: power vs. data rate at 25 mhz operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 18: data interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 19: request deasserts at eor, strobe condition of dsc=0-3, 6-15; erc=0 . . . . . . . . . . . . . . . . . . . . . . . 31 figure 20: request deasserts at eor, strobe condition of dsc=0-3, 6-15; erc=1 . . . . . . . . . . . . . . . . . . . . . . . 32 figure 21: request deasserts at eor, strobe condition of dsc=4 or 5; erc=0 . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 22: request deasserts at eor, strobe condition of dsc=4 or 5; erc=1 . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 23: output enable timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 24: video input port timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 25: video output port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 26: microprocessor interface timing (procmode[1]=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 27: microprocessor interface timing (procmode[1]=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 28: interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 29: clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 30: power on reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure a1: dma mode timing for single word writes, strobe condition of dsc=000 . . . . . . . . . . . . . . . . . . . . . . 41 figure a2: dma mode timing for single word reads, strobe condition of dsc=000 . . . . . . . . . . . . . . . . . . . . . . 41 figure a3: dma mode timing for four word burst write, one wait state, strobe condition of dsc=000. . . . . . . 41 figure a4: dma mode timing for four word burst read, one wait state, strobe condition of dsc=000 . . . . . . 42 figure a5: dma mode timing for eight word burst write, zero wait state, strobe condition of dsc=000 . . . . . . 42 figure a6: dma mode timing for eight word burst read, zero wait state, strobe condition of dsc=000 . . . . . . 42 figure a7: dma mode timing for single word writes, strobe condition of dsc=010 . . . . . . . . . . . . . . . . . . . . . . 43 figure a8: dma mode timing for single word reads, strobe condition of dsc=010 . . . . . . . . . . . . . . . . . . . . . . 43 figure a9: dma mode timing for four word burst write, one wait state, strobe condition of dsc=010. . . . . . . 43 figure a10: dma mode timing for four word burst read, one wait state, strobe condition of dsc=010 . . . . . . 44 figure a11: dma mode timing for eight word burst write, zero wait state, strobe condition of dsc=010 . . . . . . 44 figure a12: dma mode timing for eight word burst read, zero wait state, strobe condition of dsc=010 . . . . . . 44 figure a13: dma mode timing for single word writes, strobe condition of dsc=011 . . . . . . . . . . . . . . . . . . . . . . 45 figure a14: dma mode timing for single word reads, strobe condition of dsc=011 . . . . . . . . . . . . . . . . . . . . . . 45 figure a15: dma mode timing for four word burst write, one wait state, strobe condition of dsc=011. . . . . . . 45 figure a16: dma mode timing for four word burst read, one wait state, strobe condition of dsc=011 . . . . . . 46 figure a17: dma mode timing for eight word burst write, zero wait state, strobe condition of dsc=011 . . . . . . 46 figure a18: dma mode timing for eight word burst read, zero wait state, strobe condition of dsc=011 . . . . . . 46 figure a19: dma mode timing for single word writes, strobe condition of dsc=111 . . . . . . . . . . . . . . . . . . . . . . 47 figure a20: dma mode timing for single word reads, strobe condition of dsc=111 . . . . . . . . . . . . . . . . . . . . . . 47
advanced hardware architectures, inc. iv ps3410c-0600 tables table 1: data bus and fifo sizes supported by starlite tm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 table 2: starlite tm connection to host microprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 table 3: microprocessor port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 4: internal strobe conditions for dma mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 5: internal registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 6: data port timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 7: request vs. eor timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 8: output enable timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 9: video input port timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 10: video output port timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 11: microprocessor interface timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 12: interrupt timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 13: clock timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 14: power on reset timing requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
ps3410c-0600 page 1 of 47 advanced hardware architectures, inc. 1.0 introduction starlite? is a single chip cmos vlsi coprocessor device that implements a lossless compression and decompression algorithm. the algorithm exhibits an average compression ratio over 13 to 1 for bitmap image data. the device supports simultaneous compression and decom- pression operations at 25 mbytes/sec each. the device interfaces directly to various risc and cisc processors from amd, intel and motorola. compression and decompression data transfers normally occur over a high speed bidirectional 32-bit data bus capable of up to 100 mbytes/sec synchronous data rates. two 8-bit synchronous video data ports provide ability to optionally interface to scanner and print engine respectively for applications such as multifunction laser printers and copiers. a low power mode is achieved by stopping all data transfers and the clock signal. all outputs may be tristated to facilitate board level testing. this document contains functional description, system configurations, register descriptions and timing diagrams. it is intended for system designers considering a compression coprocessor in their embedded applications. software simulation and an analysis of the algorithm for printer and copier images of various complexity are also available for evaluation. a comprehensive designer?s guide complementing this document is also available from aha to assist with the system design. section 11.0 contains a list of related technical publications. 1.1 conventions, notations and definitions ? active low signals have an ?n? appended to the end of the signal name. for example, csn and rdyn. ? a ?bar? over a signal name indicates an inverse of the signal. for example, sd indicates an inverse of sd. this terminology is used only in logic equations. ? ?signal assertion? means the output signal is logically true. ? hex values are represented with a prefix of ?0x?, such as register ?0x00?. binary values do not contain a prefix, for example, dsc=000. ? a range of signal names or register bits is denoted by a set of colons between the numbers. most significant bit is always shown first, followed by least significant bit. for example, vod[7:0] indicates signal names vod7 through vod0. ? a logical ?and? function of two signals is expressed with an ?&? between variables. ? mega bytes per second is referred to as mbytes/ sec or mb/sec. ? in referencing microprocessors, an x or xx is used as suffix to indicate more than one processor. for example, am290xx processor family includes the am29000, 29005, 29030 and 29035. ? reserved bits in registers are referred as ? res ?. ? reqn or ackn refer to either ci, di, co or do request or acknowledge signals, as applicable. 1.2 features performance: 25 mb/sec compression and decompression rates 100 mb/sec burst data rate over a 32-bit data bus 25 mb/sec synchronous 8-bit video in and video out ports simultaneous compression and decompression operation at full bandwidth average 13 to 1 compression performance for bitmap image data flexibility: configurable i/o interface for dma mode; big endian or little endian; and 32-bit or 16-bit bus widths interfaces directly with am29k or i960 family of risc processors and motorola 68xxx cisc processors optional 8-bit video input and output ports pass-through mode passes raw data through compression and decompression engines optional counter enables error checking in decompression operation system interface: single chip compression and decompression solution no external sram required four 16 32-bit fifos programmable interrupts 25 mhz maximum clock frequency output signals may be tristated to facilitate board level testing others: low power modes software emulation program available 120 pin quad flat package
page 2 of 47 ps3410c-0600 advanced hardware architectures, inc. figure 1: functional block diagram 1.3 functional overview the coprocessor device has three external high speed synchronous data ports capable of transferring once every 25 mhz clock. these are a 32-bit bidirectional data port, an 8-bit video input data (vid) port and a video output data (vod) port. the 32-bit port is capable of transferring up to 100 mbytes/sec. the vid and vod are capable of up to 25 mbytes/sec each. the device accepts uncompressed data through the 8-bit vid port or the 32-bit data port into its compression in fifo (ci fifo). the 32-bit data port may be configured for 16-bit transfers. compressed data is available through the 32-bit data port via the compressed output fifo (co fifo). the sustained data rate through the compression engine is 25 mbytes/sec. decompression data may be simultaneously processed by the device. decompression data is accepted through the 32-bit data port, buffered in the decompression input fifo (di fifo) and decompressed. the output data is made available on the 32-bit data port via the decompression output fifo (do fifo) or the 8-bit video output port. the decompression engine runs on the 25 mhz clock and is capable of processing an uncompressed byte every clock, i.e., 25 mb/sec. the four fifos are organized as 16 32 each. for data transfers through the three ports, the ? effective ? fifo sizes differ according to their data bus widths. the table below shows the size of the data port and the ? effective ? fifo size for the various configurations supported by the device. table 1: data bus and fifo sizes supported by starlite tm (from scanner) vireqn vid[7:0] viackn d[31:0] driven test clk rstn procmode[1:0] pd[7:0] pa[4:0] csn dir rdyn intrn voackn vod[7:0] voreqn voeorn (to printer) coeorn doreqn coreqn direqn cireqn sd doackn coackn diackn ciackn vid port data port ci fifo 16x32 di fifo 16x32 clock data port control compressor decompressor microprocessor interface co fifo 16x32 do fifo 16x32 vod port aha3410c starlitetm 8 8 8 8 8 8 32 32 32 5 8 operation data bus width port effective fifo size compression data in 8 video in 16 8 compression data in/out 32 data port 16 32 compression data in/out 16 data port 16 16 decompression data in/out 32 data port 16 32 decompression data in/out 16 data port 16 16 decompressed data out 8 video out 16 8
ps3410c-0600 page 3 of 47 advanced hardware architectures, inc. table 2: starlite tm connection to host microprocessors movement of data for compression or decompression is performed using synchronous dma over the 32-bit data port. the video ports support synchronous dma mode transfers. the dma strobe conditions are configurable for the 32- bit data port depending upon the risc processor of the system and the dma controller available. data transfer for compression or decompression is synchronous over the three data ports functioning as dma masters. to initiate a transfer into or out of the video ports, the device asserts vxreqn, the external device responds with vxackn and begins to transfer data over the vid or vod busses on each succeeding rising edge of the clock until vxreqn is deasserted. the 32-bit port relies on the fifo threshold settings to determine the transfer. the sections below describe the various configurations, programming and other special considerations in developing a compression system using starlite tm . 2.0 system configuration this section provides information on connecting starlite tm to various microprocessors in dma mode. 2.1 microprocessor interface the device is capable of interfacing directly to various processors for embedded application. the table below shows how starlite tm should be connected to various host microprocessors. all register accesses to starlite tm are performed on the 8-bit pd bus. the pd bus is the lowest byte of the 32-bit microprocessor bus. during reads of the internal registers, the upper 24 bits are not driven. system designers should terminate these lines with pullup resistors. starlite tm provides four modes of operation for the microprocessor port. both active high and active low write enable signals are allowed as well as two modes for chip select. the mode of operation is set by the procmode[1:0] pins. the procmode[1] signal selects when csn must be active and also how long an access lasts. when procmode[1] is high, csn determines the length of the access. csn must be at least 5 clocks in length. on a read, valid data is driven onto pd[7:0] during the 5th clock. if csn is longer than 5 clocks, then valid data continues to be driven out onto pd[7:0]. when csn goes inactive (high), pd[7:0] goes tristate (asynchronously) and rdyn is driven high asynchronously. csn must be high for at least two clocks. rdyn is always driven (it is not tristated when procmode[1] is high). the mode is typical of processors such as the motorola 68xxx. when procmode[1] is low, accesses are fixed at 5 clocks, pd[7:0] is only driven during the fifth clock, and rdyn is driven high for the first 4 clocks and low during the fifth clock. rdyn is tristated at all other times. write data must be driven the clock after csn is sampled low. accesses may be back to back with no delays in between. this mode is typical of risc processors such as the i960 and am29k. procmode[0] determines the polarity of the dir pin. if procmode[0] is high, then the dir pin is an active low write enable. if procmode[0] is low, then the dir pin is an active high write enable. figure 2 through figure 5 illustrate the detailed timing diagrams for the microprocessor interface. for additional notes on interfacing to various microprocessors, refer to aha application note (andc12), starlite tm designer?s guide . pin name am290xx am292xx i960cx i960kx pa a a a lad csn cs piacs cs cs dir r/w r/w w/r w/r pd d id d lad sd vdd vdd wa i t ready rdyn drdy no connect no connect ready driven system dependent piaoe den system dependent clock sysclk memclk pclk no connect
page 4 of 47 ps3410c-0600 advanced hardware architectures, inc. table 3: microprocessor port configuration figure 2: microprocessor port write (procmode[1:0]=?01?) figure 3: microprocessor port read (procmode[1:0]=?01?) procmode[1:0] dir cycle length example processor 00 active high write fixed i960 01 active low write fixed am29k 10 active high write variable 11 active low write variable 68xxx clock pa[4:0] csn dir pd[7:0] a0 rdyn a1 d0 d1 clock pa[4:0] csn dir pd[7:0] a0 rdyn a1 d0 a2 d1
ps3410c-0600 page 5 of 47 advanced hardware architectures, inc. figure 4: microprocessor port write (procmode[1:0]= ? 11 ? ) figure 5: microprocessor port read (procmode[1:0]= ? 11 ? ) clock pa[4:0] csn dir pd[7:0] a0 rdyn a1 d0 clock pa[4:0] csn dir pd[7:0] a0 rdyn a1 d0
page 6 of 47 ps3410c-0600 advanced hardware architectures, inc. 3.0 functional description this section describes the various data ports, special handling, data formats and clocking structure. 3.1 data ports starlite tm contains two data input ports, ci and di, and two data output ports, co and do on the same 32-bit data bus, d[31:0]. data transfers can be controlled by an external dma control. the logical conditions under which data is written to the input fifos or read from the output fifos are set by the dsc (data strobe condition) field of the system configuration 1 register. a strobe condition defines under what logical conditions the input fifos are written or the output fifos read. ciackn, coackn, diackn, doackn, and sd pins combine to strobe data in a manner similar to dma controllers. the dma mode sub-section describes the various data strobe options. 3.2 dma mode dma data strobes are indicated by setting the most significant bit of the data strobe condition to zero (dsc[3]=0). on the rising edge of clock when the strobe condition is met, the port with the active acknowledge either strobes data into or out of the chip. no more than one port may assert acknowledge at any one time. table 4 shows the various conditions that may be programmed into register dsc. figure 6 through figure 11 illustrate the dma mode timings for single, four word and eight word burst transfers for dsc=100 selection. for other dsc settings, please refer to appendix a. note that the only difference between odd and even values of dsc is the polarity of sd. waveforms are only shown for polarities of sd corresponding to specific systems. table 4: internal strobe conditions for dma mode dsc[3:0] logic equation system configuration 0000 i960cx with internal dma controller. sd is connected to wa i t n . 0001 no specific system 0010 general purpose dma controller 0011 i960kx or am290xx with external, bus master type dma controller. sd is connected to rdyn. 0100 am2924x with internal dma controller 0101 no specific system 0110 am2920x with internal dma controller 0111 am2920x with internal dma controller ackn () & ackn delayed () & sd () ackn () & ackn delayed () & sd () ackn () & sd () ackn () & sd () ackn delayed () & sd delayed () ackn delayed () & sd delayed () ackn () & ackn delayed () ackn () & ackn delayed () ackn delayed ackn delayed 1 clock = sd delayed sd delayed 1 clock =
ps3410c-0600 page 7 of 47 advanced hardware architectures, inc. figure 6: dma mode timing for single word writes, strobe condition of dsc=100 figure 7: dma mode timing for single word reads, strobe condition of dsc=100 figure 8: dma mode timing for four word burst write, one wait state, strobe condition of dsc=100 clock ackn sd driven d d0 d1 clock ackn sd driven d d1 d0 clock ackn sd driven d d0 d2 d1 d3
page 8 of 47 ps3410c-0600 advanced hardware architectures, inc. figure 9: dma mode timing for four word burst read, one wait state, strobe condition of dsc=100 figure 10: dma mode timing for eight word burst write, zero wait state, strobe condition of dsc=100 figure 11: dma mode timing for eight word burst read, zero wait state, strobe condition of dsc=100 clock ackn sd driven d d1 d0 d2 d3 clock ackn sd driven d d0 d2 d1 d3 d4 d5 d6 d7 clock ackn sd driven d d0 d2 d1 d3 d4 d5 d6 d7
ps3410c-0600 page 9 of 47 advanced hardware architectures, inc. 3.3 pad word handling in burst mode if a word containing an end-of-record comes out during a burst read, the words after the end-of- record are invalid (pad) words. this prevents a burst read from crossing record boundaries. the first word of the next burst read is the first word of the next record. the pad words must be deleted during decompression by using the decompression pause on record boundaries bit (dpor), in the decompression control register. after the part is paused, the di fifo must be reset by asserting the dirst bit in the port control register. decompressor must also be reset by asserting ddr bit in decompression control register. the coeorn signal is asserted when an end- of-record is present on the output of the co fifo. coeorn is active while the eor is strobed out. in some systems coeorn can be used to generate a dma-done condition. 3.4 dma request signals and status starlite tm requests data using request pins (cireqn, direqn, coreqn, doreqn). the requests are controlled by programmable fifo thresholds. both input and output fifos have programmable empty and full thresholds set in the input fifo threshold and output fifo threshold registers. by requesting only when a fifo can sustain a certain burst size, the bus is used more efficiently. the input requests, cireqn and direqn, operate under the following prioritized rules: 1) if the fifo reset in the port control register is active, the request is inactive. 2) if a fifo overflow interrupt is active, the request is inactive. 3) if the fifo is at or below the empty threshold, the request will go active. 4) if the fifo is at or above the full threshold, the request will go inactive. the output requests, coreqn and doreqn, operate under the following prioritized rules: 1) if the fifo reset in the port control register is active, the request is inactive. 2) if the output fifo underflow interrupt is active, the request is inactive. 3) if an eor is present in the output fifo, the request will go active. 4) if the output fifo is at or above the full threshold, the request will go active. 5) if an eor is read (strobed) out of the fifo, the request will go inactive during the same clock as the strobe (if erc=0), otherwise it will go inactive on the next clock. 6) if the output fifo is at or below the empty threshold, the request will go inactive. 3.4.1 fifo thresholds for maximum efficiency, the fifo thresholds should be set in such a way that the compressor seldom runs out of data from the ci fifo or completely fills the output fifo. the fifos are 16 words deep. for example, in a system with fixed 8-word bursts, good values for the thresholds are: iet=3, ift=4, oft=d, oet=c setting the input full threshold to one higher than the input empty threshold simply guarantees that the request will deassert as soon as possible. the latency between a word being strobed in and the request changing due to a fifo threshold condition is 3 clocks. this should be kept in mind when programming threshold values. refer to aha application note (andc12), starlite tm designer ? s guide for a more thorough discussion of fifo thresholds. the following figure shows an example of an input fifo crossing its full threshold.
page 10 of 47 ps3410c-0600 advanced hardware architectures, inc. figure 12: fifo threshold example (ift=4, dsc=2, 1 word already in fifo) note: cireqn deasserted when threshold counter exceeded ift=4. figure 13: request vs. end-of-record, strobe condition of dsc=010 3.4.2 request during an end-of-record the request deasserts at an eor in one of two ways. if erc bit in system configuration 1 is ? 0 ? , the request will deassert asynchronously during the clock where the eor is strobed out of the fifo. this leads to a long output delay for reqn, but may be necessary in some systems. for dsc values of 4 or 5, the request deasserts the first clock after the acknowledge pulse for the eor. if erc is set to ? 1 ? , then the request deasserts synchronously the clock after the eor is strobed out. the minimum low time on the request in this case is one clock. the request delay varies between the different strobe conditions. see the timing section for further details. 3.4.3 request status bits an external microprocessor can also read the value of each request using the cireq and coreq bits in the compression port status register and the direq and doreq bits in the decompression port status register. please note that the request status bits are active high while the pins are active low. clock d ciackn cireqn threshold 1 2 3 45 6 7 8 1 23 4 5 6 78 9 counter eor-2 clock d ackn reqn eor-1 eor (erc=0) reqn (erc=1)
ps3410c-0600 page 11 of 47 advanced hardware architectures, inc. 3.5 data format the width of the d bus is selected with the wide bit in system configuration 0 . if wide=1, then d is a 32-bit bus. if wide=0, d is a 16-bit bus. if the bus is configured to be 16-bits wide (wide=0), all data transfers occur on d[15:0] and the upper 16 bits of the bus, d[31:16], should be terminated with pullup resistors. if wide=0, the fifo is sixteen words deep. since the compression algorithm is byte oriented, it is necessary for starlite tm to know the ordering of the bytes within the word. the big bit in system configuration 0 selects between big endian and little endian byte ordering. little endian stores the first byte in the lower eight bits of a word (d[7:0]). big endian stores the first byte in the uppermost eight bits of a word (d[31:24] for wide=1, d[15:8] for wide=0). 3.6 odd byte handling all data transfers to or from either the compression or decompression engines are performed on the d bus on word boundaries. since no provision is made for single byte transfers, occasionally words will contain pad bytes. following is a description of when these pad bytes are necessary for each of the data interfaces. 3.6.1 compression input and pad bytes uncompressed data input into starlite tm is treated as records. the length of these records is fixed by the value in the record length or rlen register. this register contains the number of uncompressed bytes in each record. if the value in rlen is not an integer multiple of number of bytes per word as selected by wide, the final word in the transfer of the record will contain pad bytes which are discarded and have no effect on either the dictionary or the output data stream. the next record must begin on a word boundary. the minimum value for rlen is 4. 3.6.2 compression output and pad bytes if a record ends on a byte other than the last byte in a word, the final word will contain 1, 2 or 3 pad bytes. the pad bytes have a value of 0x00. 3.6.3 decompression input, pad bytes and error checking this port recognizes the end of a record by the appearance of a special end-of-record sequence in the data stream. once this is seen, the remaining bytes in the current word are treated as pad bytes and discarded. the word following the end of the record is the beginning of the next record. when operating in decompression mode, the decompression record length (drlen) register can be used to provide error checking. the expected length of the decompressed record is programmed into the drlen register. the decompressor then counts down from the value in drlen to ? 0 ? . a derr interrupt is issued if an eor is not read out of the decompressor when the counter expires or if an eor occurs before the counter expires (i.e., when the record lengths do not match). if the derr interrupt is masked, use of the drlen register is optional. when operating in pass-through mode, there is no end-of-record codeword for the decompressor to see. in pass-through mode, the user must set the record length in the drlen register. 3.6.4 decompression output and pad bytes when the decompressor detects an end-of- record codeword, it will add enough pad bytes of value 0x00 to complete the current word.
page 12 of 47 ps3410c-0600 advanced hardware architectures, inc. 3.7 video interfaces 3.7.1 video input the video input port is enabled by the vdie bit in the system configuration 1 register. the port uses vireqn to indicate that the port can accept another byte. the value on vid[7:0] is written into starlite tm each clock that vireqn and viackn are both low. the video input port asserts vireqn whenever there is room in the ci fifo. the values in iet and ift are all ignored. the compression input fifo is 16 bytes deep in this mode. the video input port can transfer up to one byte per clock (25 mb/sec). the dma interface cannot access the compression input fifo when vdie is set. 3.7.2 video output the video output port is enabled by the vdoe bit in the system configuration 1 register. the port uses voreqn to indicate that the byte on vod[7:0] is valid. an 8-bit word is read each clock when both voreqn and voackn are sampled low on a rising edge of clock. pad bytes at an end of record are discarded by the video output port and do not appear on vod[7:0]. when the byte on vod[7:0] is the last byte in a record, the voeorn signal will go low. voeorn is active while an eor is read out. unlike a dma transfer, there are no pad bytes after an end-of-record. the port requests whenever a valid byte is present on the output. the values in oet and oft are all ignored. the decompression output fifo is 16 bytes deep in this mode. the video output port can output up to one byte per clock (25 mb/sec). the dma interface cannot access the decompression output fifo when vdoe is set. figure 14: timing diagram, video input figure 15: timing diagram, video output clock vireqn viackn vid[7:0] 0 3 don ? t care 1 2 don ? t care 4 5 don ? t care clock voreqn voackn vod[7:0] 0 3 1 2 4 5 voeorn
ps3410c-0600 page 13 of 47 advanced hardware architectures, inc. 3.8 compression engine the compression engine supports either compression or pass-through processes. the compression engine is enabled with the comp bit in the compression control register. when the engine is enabled, it takes data from the ci fifo as it becomes available. this data is either compressed by the engine or passed through unaltered. this pass-through mode is selected with the cpass bit in the compression control register. the cpass bit may only be changed when comp is set to ? 0 ? . the contents of the dictionary are preserved when comp is changed. however, when cpass is changed, the contents are lost. consequently, starlite tm can not be changed from pass-through mode to compression mode or vice versa without losing the contents of the dictionary. the compressor can be instructed to halt input at the end of each record. if the cpor bit is set, the compressor will stop taking bytes out of the ci fifo immediately after the last byte of a record. in addition, the comp bit will be cleared. the cemp bit will then indicate when all of the data has left the compressor. compression is restarted by setting the comp bit. the compression engine takes data from the compression input fifo at a maximum rate of 25 mbytes/sec. two conditions cause the data rate to drop below the maximum. the first is caused by the compression input fifo running empty of data to be compressed. the second condition is caused by the output fifo filling. when this occurs, the engine halts and waits for the fifo. while halted, the engine goes into a low power standby mode. refer to the table in section 7.1 for the extent of power savings. 3.9 decompression engine the decompression engine is enabled with the dcomp bit in the decompression control register. when the engine is enabled, it takes data from the di fifo as it becomes available. this data is either decompressed by the engine or passed through unaltered. pass-through mode is selected with the dpass bit. dpass may only be changed when dcomp is set to ? 0 ? and demp is set to ? 1 ? . the contents of the dictionary are preserved when dcomp is changed. however, when dpass is changed, the contents are lost. consequently, starlite tm can not be changed from pass-through mode to decompression mode or vice versa without losing the contents of the dictionary. the decompressor can be instructed to halt operation at the end of each record. if the dpor bit is set, the decompressor will stop processing additional data after it decodes an end-of-record and dcomp will be cleared. if dpor is set and data from a second record enters the fifo immediately after the first record, bytes from the second record will have entered the decompressor prior to decoding the eor. an implication of this is that bytes from the second record will remain in the decompressor and prevent demp from setting after all of the data from the first record has left the decompressor. this differs from operation of the compression engine. in either mode, a doeor interrupt is generated when the last byte of a compressed record is read out of the chip. the decompressor takes data from the decompression input fifo at a maximum rate of 25 mbytes/sec. starlite tm can maintain this data rate as long as the decompression input fifo is not empty or the decompression output fifo is not full. 3.10 interrupts seven conditions are reported in the interrupt status/control register as individual bits. all interrupts are maskable by setting the corresponding bits in the interrupt mask register. a ? 1 ? in the interrupt mask register means the corresponding bit in the interrupt status/control register is masked and does not affect the interrupt pin (intrn). the intrn pin is active whenever any unmasked interrupt bit is set to a ? 1 ? . end-of-record interrupts are posted when a word containing an end-of-record is strobed out of the compression or decompression output fifos (ceor and deor respectively). a deor interrupt is also reported if an end-of-record is read from the video output port. four fifo error conditions are also reported. overflowing the input fifos generates a ciof or diof interrupt. an overflow can only be cleared by resetting the respective fifo via the port control register. underflowing the output fifos (reading when they are not ready) generates a couf or douf. underflow interrupts are cleared by writing a ? 1 ? to couf or douf. in the event of an underflow, the respective fifo must be reset. note that in systems using fixed length bursts which rearbitrate during a burst, the co fifo may request another burst when the record actually finishes near the end of the current burst. in this scenario a second burst takes place causing a fifo underflow. as long as a pause on end-of-record is used, data is not corrupted. the fifo simply must be reset.
page 14 of 47 ps3410c-0600 advanced hardware architectures, inc. 3.11 low power mode the aha3410c is a data-driven system. when no data transfers are taking place, only the clock and on-chip rams including the fifos require power. to reduce power consumption to its absolute minimum, the user can stop the clock when it is high. with the system clock stopped and at a high level, the only current required is due to leakage. control and status registers are preserved in this mode. reinitialization of control registers are not necessary when switching from low power to normal operating mode. 3.12 test mode in order to facilitate board level testing, the aha3410c provides the ability to tristate all outputs. when the test pin is high, all outputs of the chip are tristated. when test is low, the chip returns to normal operation.
ps3410c-0600 page 15 of 47 advanced hardware architectures, inc. 4.0 register descriptions the microprocessor configures, controls and monitors ic operation through the use of the registers defined in this section. all write registers are readable with the exception of record length registers. all registers are reset to ? 0 ? on rstn unless otherwise stated. the bits labeled ? res ? are reserved and must be set to ? 0 ? when writing to registers unless otherwise noted. a summary of registers is listed below. table 5: internal registers address r/w description function default after rstn 00 r/w system configuration 0 big endian vs. little endian, 32- bit vs. 16-bit undefined 01 r/w system configuration 1 data strobe condition, eor request control, vdo port enable, vdi port enable 0x00 02 r/w input fifo thresholds input fifos empty threshold, full threshold undefined 03 r/w output fifo thresholds output fifos empty threshold, full threshold undefined 04 r compression ports status fifo status, request status, eor status undefined 05 r decompression ports status fifo status, request status, eor status undefined 06 r/w port control reset individual fifos 0x0f 07 r/w interrupt status/control eor, overflow, underflow 0x00 09 r/w interrupt mask interrupt mask bits 0xff 0a r version die version number 0x21 0c r/w decompression record length 0 bytes remaining in transfer, byte 0 0xff 0d r/w decompression record length 1 " " , byte 1 0xff 0e r/w decompression record length 2 " " , byte 2 0xff 0f r/w decompression record length 3 " " , byte 3 0xff 10 r/w record length 0 length of uncompressed data in bytes, byte 0 undefined 11 r/w record length 1 " " , byte 1 undefined 12 r/w record length 2 " " , byte 2 undefined 13 r/w record length 3 " " , byte 3 undefined 14 r/w compression control pause on record boundaries, enable compression, compres- sion engine empty status, com- pression dictionary reset, select pass-through mode 0x04 15 r/w compression reserved for production testing only 0x00 16 r/w compression configuration 0 line length register lower 8 bits undefined 17 r/w compression configuration 1 line length register upper 3 bits undefined
page 16 of 47 ps3410c-0600 advanced hardware architectures, inc. 4.1 system configuration 0, address 0x00 - read/write this register is not cleared by reset and must be initialized prior to any data transfer. x wide - selects between 32 and 16-bit d buses. big - select between little and big endian data orders. the least significant bit in a byte is always in position ? 0 ? . 18 r/w decompression control pause on record boundaries, enable decompression engine, decompression engine empty status, dictionary reset, enable pass-through mode 0x04 1a r/w decompression reserved for production testing only 0x00 1c r/w decompression configuration 0 line length register lower 8 bits undefined 1d r/w decompression configuration 1 line length register upper 3 bits undefined address (hex) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00 big wide res res big wide description 0 0 little endian data order 16-bit words d[15:8] d[7:0] byte 1 byte 0 0 1 little endian data order 32-bit words d[31:24] d[23:16] d[15:8] d[7:0] byte 3byte 2byte 1byte 0 1 0 big endian data order 16-bit words d[15:8] d[7:0] byte 0 byte 1 1 1 big endian data order 32-bit words d[31:24] d[23:16] d[15:8] d[7:0] byte 0byte 1byte 2byte 3 address r/w description function default after rstn
ps3410c-0600 page 17 of 47 advanced hardware architectures, inc. 4.2 system configuration 1, address 0x01 - read/write this register is cleared by reset. dsc[3:0] - data strobe condition. control the condition used to strobe data into and out of the data ports on the d bus. table 4 shows the programming for the strobe condition for dma data transfer modes. erc - eor request control. determines when coreqn and doreqn deassert at an end-of- record. if erc=0 then the request deasserts asynchronously during the clock when an eor is strobed out. if erc=1 then the request deasserts synchronously the clock after an eor is strobed out. see figure 19. vdoe - vdo port enable. when this bit is set, the data from the decompression output fifo goes to the vdo port. when the bit is clear, the decompressed data is read by dma on the d bus. vdie - vdi port enable. when this bit is set, the vdi port will handshake data and write it into the compression input fifo. when the bit is clear, the compression input fifo is written by dma from the d bus. 4.3 input fifo thresholds, address 0x02 - read/write this register is readable and writable. after reset, its contents are undefined. it must be written before any input or output data movement may be performed. iet[3:0] - empty threshold for input fifos. if the number of words in the input fifo (ci or di) is less than or equal to this number, the request for that channel will be asserted. ift[3:0] - full threshold for input fifos. if the number of words in the input fifo (ci or di) is greater than or equal to this number, the request for the channel is deasserted. 4.4 output fifo thresholds, address 0x03 - read/write this register is readable and writable. after reset, its contents are undefined. it must be written before any input or output data movement may be performed. oet[3:0] - empty threshold for output fifos. if the number of words in the output fifo (co or do) is less than or equal to this number, the request for the channel will be deasserted (except in the case of an end-of-record). oft[3:0] - full threshold for output fifos. if the number of words in the output fifo (co or do) is greater than or equal to this number, the request for that channel will be asserted. address (hex) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 01 res vdie vdoe erc dsc[3:0] address (hex) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 02 ift[3:0] iet[3:0] address (hex) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 03 oft[3:0] oet[3:0]
page 18 of 47 ps3410c-0600 advanced hardware architectures, inc. 4.5 compression ports status, address 0x04 - read only this is a read only register. writing to this register has no effect. after reset, its contents are undefined. cift - compression input fifo full threshold. this signal is active when the ci fifo is greater than or equal to the programmed fifo full threshold. after reset and the input fifo threshold register has been written, this bit contains a ? 0 ? . cireq - compression input request signal state. reports the current state for the cireqn pin. notice that this bit is active high while the pin is active low. therefore, the value of this bit will always be the inverse of the value of the signal. after reset this bit contains a ? 0 ? . coet - compression output fifo empty threshold. this signal is active when the co fifo is less than or equal to the programmed fifo empty threshold. after reset and the output fifo threshold register has been written, this bit contains a ? 1 ? . coreq - compression output request signal state. reports the current state for the coreqn pin. notice that this bit is active high while the pin is active low. therefore, the value of this bit will always be the inverse of the value of the signal. after reset this bit contains a ? 0 ? . coeor - compression output end of record. this signal is active when the output fifo contains the end- of-record code. after reset this bit contains a ? 0 ? . ciemp - compression input empty. this bit is active when the ci fifo is empty. after reset this bit contains a ? 1 ? . coemp - compression output empty. this bit is active when the co fifo is empty. after reset this bit contains a ? 1 ? . 4.6 decompression ports status, address 0x05 - read only this is a read only register. writing to this register has no effect. after reset, its contents are undefined. dift - decompression input fifo full threshold. this signal is active when the di fifo is at or above the programmed fifo full threshold. after reset and the input fifo threshold register has been written, this bit contains a ? 0 ? . direq - decompression input request signal state. reports the current state for the direqn pin. notice that this bit is active high while the pin is active low. therefore, the value of this bit will always be the inverse of the value of the signal. after reset this bit contains a ? 0 ? . doet - decompression output fifo empty threshold. this signal is active when the do fifo is at or below the programmed fifo empty threshold. after reset and the output fifo threshold register has been written, this bit contains a ? 1 ? . doreq - decompression output request signal state. reports the current state for the doreqn pin. notice that this bit is active high while the pin is active low. therefore, the value of this bit will always be the inverse of the value of the signal. after reset this bit contains a ? 0 ? . doeor - decompression output end of record. this signal is active when the output fifo contains the end-of-record code. after reset this bit contains a ? 0 ? . diemp - decompression input empty. this bit is active when the di fifo is empty. after reset this bit contains a ? 1 ? . doemp - decompression output empty. this bit is active when the do fifo is empty. after reset this bit contains a ? 1 ? . address (hex) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 04 coemp ciemp res coeor coreq coet cireq cift address (hex) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 05 doemp diemp res doeor doreq doet direq dift
ps3410c-0600 page 19 of 47 advanced hardware architectures, inc. 4.7 port control, address 0x06 - read/write this register is initialized to ? 0f ? after reset. cirst - compression input reset. setting this bit to a ? 1 ? resets the ci fifo and clears state machines on the compression input port. the reset condition will remain active until the microprocessor writes a ? 0 ? to this bit. corst - compression output reset. setting this bit to a ? 1 ? resets the co fifo and clears state machines on the compression output port. the reset condition will remain active until the microprocessor writes a ? 0 ? to this bit. dirst - decompression input reset. setting this bit to a ? 1 ? resets the di fifo and clears the state machines in the decompression input port. the reset condition will remain active until the microprocessor writes a ? 0 ? to this bit. dorst - decompression output reset. setting this bit to a ? 1 ? resets the do fifo and clears the state machines in the decompression output port. the reset condition will remain active until the microprocessor writes a ? 0 ? to this bit. 4.8 interrupt status/control, address 0x07 - read/write this register is initialized to ? 00 ? after reset. ceor - compression end-of-record interrupt. this bit is set when an end-of-record codeword is strobed out of the compression output port. to clear this interrupt the microprocessor must write a ? 1 ? to this bit. deor - decompression end-of-record interrupt. this bit is set when the last byte of a record is strobed out of the decompression dma or video output port. to clear this interrupt the microprocessor must write a ? 1 ? to this bit. derr - decompression error. this bit is set if an eor leaves the decompressor before drlen has counted down to zero or if drlen counts to zero and the last byte is not an eor. derr is only active in decompression mode (dpass=0). to clear this interrupt, the microprocessor must write a ? 1 ? to this bit. ciof - compression input fifo overflow. this interrupt is generated when a write to the ci fifo is performed when it is full. all data written when the fifo is full is lost. the only means of recovery from this error is to reset the fifo with the cirst bit. resetting the fifo causes this interrupt to clear. while the interrupt is set cireqn is inactive. diof - decompression input fifo overflow. this interrupt is generated when a write to the di fifo is performed when it is full. all data written when the fifo is full is lost. the only means of recovery from this error is to reset the fifo with the dirst bit. resetting the fifo causes this interrupt to clear. while the interrupt is set direqn is inactive. address (hex) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 06 res dorst dirst corst cirst address (hex) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 07 douf couf diof ciof res derr deor ceor
page 20 of 47 ps3410c-0600 advanced hardware architectures, inc. couf - compression output fifo underflow. this interrupt is generated when a read from the co fifo is performed when it is empty. once this interrupt is set, the co fifo must be reset with the corst bit. to clear this interrupt the microprocessor must write a ? 1 ? to this bit. while the interrupt is set, coreqn is inactive. douf - decompression output fifo underflow. this interrupt is generated when a read from the do fifo is performed when it is empty. once this interrupt is set, the do fifo must be reset with the dorst bit. to clear this interrupt the microprocessor must write a ? 1 ? to this bit. while the interrupt is set, doreqn is inactive. 4.9 interrupt mask, address 0x09 - read/write this register is initialized to ? ff ? after reset. ceorm - compression end-of-record interrupt mask. when set to a ? 1 ? , prevents compression end-of- record from causing intrn to go active. deorm - decompression end-of-record interrupt mask. when set to a ? 1 ? , prevents decompression end-of-record from causing intrn to go active. derrm - decompression error mask. when set to a ? 1 ? , prevents a decompression error (derr) from causing intrn to go active. ciofm - compression input fifo overflow mask. when set to a ? 1 ? , prevents a compression input fifo overflow (ciof) from causing intrn to go active. diofm - decompression input fifo overflow mask. when set to a ? 1 ? , prevents a decompression input fifo overflow (diof) from causing intrn to go active. coufm - compression output fifo underflow mask. when set to a ? 1 ? , prevents a compression output fifo underflow (couf) from causing intrn to go active. doufm - decompression output fifo underflow mask. when set to a ? 1 ? , prevents a decompression output fifo underflow (douf) from causing intrn to go active. 4.10 version, address 0x0a - read only this is a read only register. writing to this register has no effect on ic operation. version[7:0] - contains version number of the die. initial version is 0x21. address (hex) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 09 doufm coufm diofm ciofm res derrm deorm ceorm address (hex) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0a version[7:0]
ps3410c-0600 page 21 of 47 advanced hardware architectures, inc. 4.11 decompression record length, address 0x0c, 0x0d, 0x0e, 0x0f - read/write these registers are initialized to ? ff ? after reset. drlen[31:0]-decompression record length. contains the number of bytes in a decompressed record. these registers provide different functions depending on whether the decompressor is in pass- through or decompression mode. in decompress mode, the data itself contains eor information and drlen is only used for error checking. drlen is decremented each time a byte leaves the decompressor. in decompression mode, a derr interrupt is issued if an eor is not read out of the decompressor when the counter expires or if an eor occurs before the counter expires (i.e., when the record lengths do not match). if the derr interrupt is masked, use of the drlen register is optional in decompression mode. in pass-through mode, drlen determines the size of records read out of the decompressor. the counter is decremented for each byte read into the decompressor. in either mode, the counter reloads when it reaches zero or when drlen[31:24] is written. reading drlen returns the number of bytes left in the count. 4.12 record length, address 0x10, 0x11, 0x12, 0x13 - read/write these registers are undefined after reset. rlen[31:0]- record length. length of an uncompressed record in bytes. writing these addresses sets a register containing the length of a record. reading these addresses returns a counter indicating the number of bytes remaining in the current record. the counter is decremented each time a byte leaves the ci fifo. the counter automatically reloads from the register at the end of a record. the counter is also reloaded when rlen[31:24] is written. the record length register is also valid during pass-through operation. the minimum value for rlen is 4. address (hex) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0c drlen[7:0] 0d drlen[15:8] 0e drlen[23:16] 0f drlen[31:24] address (hex) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 10 rlen[7:0] 11 rlen[15:8] 12 rlen[23:16] 13 rlen[31:24]
page 22 of 47 ps3410c-0600 advanced hardware architectures, inc. 4.13 compression control, address 0x14 - read/write this register is initialized to ? 04 ? after reset. cpor - compression pause on record boundaries. when this bit is set to ? 1 ? , the compressor stops taking data from the input fifo once a record boundary is found. a record boundary is indicated by the rlen register decrementing to ? 0 ? . upon finding the record boundary, comp is cleared. this bit may only be changed when comp is set to ? 0 ? . after system reset, this bit is cleared. comp - compression. setting this bit to a ? 1 ? enables the data compression engine (or pass-through mode if cpass is set) to take data from the compression input fifo. if this bit is cleared, compression stops. the bit is automatically cleared at the end of a record if cpor is set. the compression can be restarted without loss of data by setting comp. after reset, this bit is cleared. cemp - compression engine empty. this bit is set to a ? 1 ? when no data is present inside the compressor. writing to this bit has no effect. after system reset, this bit is set. cdr - compression dictionary reset. setting this bit immediately resets the compressor including the compression dictionary. the reset condition will remain active until the microprocessor writes a ? 0 ? to this bit. cpass - compression pass-through mode. while this bit is set, data is passed directly through the compression engine without any effect on either the dictionary or the data itself. this bit may only be changed when compression is disabled (comp=0) and the compression engine is empty of data (cemp=0). the pass-through operation is started by setting comp. to stop the pass- through operation, comp should be cleared (to pause operation) and then cpass may be cleared. bit[5] - reserved. set to ? 0 ? . bit[7:6] - reserved. set to ? 0 ? . 4.14 compression reserved, address 0x15 - read/write this register is used for production testing. must be written with ? 0 ? if at all. resets to ? 0 ? . 4.15 compression configuration, address 0x16, 0x17 - read/write this register contains information necessary for the compression operation. it must be set prior to any compression operation. it should only be changed when comp is cleared and cemp is set. after changing compression configuration, the compressor should be reset using cdr. these registers are undefined after reset. line[10:0]-line length. the number of bytes in the scan line is programmed here. minimum value is 16. address (hex) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 14 res cpass cdr cemp comp cpor address (hex) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 15 res address (hex) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 16 line[7:0] 17 res line[10:8]
ps3410c-0600 page 23 of 47 advanced hardware architectures, inc. 4.16 decompression control, address 0x18 - read/write this register is initialized to ? 04 ? after reset. dpor - decompression pause on record boundaries. when this bit is set to ? 1 ? , the decompressor stops taking data from the input fifo once a record boundary is found. upon finding the record boundary, dcomp is cleared. this bit may only be changed when dcomp is set to ? 0 ? . after system reset or ddr, this bit is cleared. dcomp - decompression. setting this bit to a ? 1 ? enables the decompression engine (or pass-through mode if dpass is set) to take data from the decompression input fifo. if this bit is cleared, decompression stops. the bit is automatically cleared at the end of a record if dpor is set. decompression can be restarted without loss of data by setting dcomp. after system reset or ddr, this bit is cleared. demp - decompression engine empty. this bit is set when the decompression engine is cleared of data. writing to this bit has no effect. after system reset, this bit is set. ddr - decompression dictionary reset. setting this bit immediately resets the decompressor including the decompression dictionary. the reset condition will remain active until the microprocessor writes a ? 0 ? to this bit. dpass - decompression pass-through mode. while this bit is set, data is passed directly through the decompression engine without any effect on the data. this bit may only be changed when decompression is disabled (dcomp=0) and the decompression engine is empty of data (demp=1). the pass-through operation is started by setting dcomp. to stop the pass-through operation, dcomp should be cleared (to pause operation) and then dpass may be cleared. 4.17 decompression reserved, address 0x1a - read/write this register is used for production testing only. must be written with ? 0 ? if at all. initialized to ? 00 ? after reset. 4.18 decompression configuration, address 0x1c, 0x1d - read/write this register contains information necessary for the decompression operation. it must be set prior to any decompression operation. it should only be changed between records when dcomp is cleared and demp is set. these registers are undefined after reset. line[10:0]-line length. the number of bytes in the scan line is programmed here. minimum value is 16. for scan line lengths larger than the maximum allowed, set to 16. address (hex) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 18 res dpass ddr demp dcomp dpor address (hex) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1a res address (hex) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1c line[7:0] 1d res line[10:8]
page 24 of 47 ps3410c-0600 advanced hardware architectures, inc. 5.0 signal descriptions this section contains descriptions for all the pins. each signal has a type code associated with it. the type codes are described in the following table. 5.1 microprocessor interface type code description i input only pin o output only pin i/o input/output pin s synchronous signal a asynchronous signal microprocessor interface signal type description pd[7:0] i/o s processor data. data for all microprocessor reads and writes of registers within starlite tm are performed on this bus. this bus may be tied to the data bus, d[31:0], provided microprocessor accesses do not occur at the same time as dma accesses. pa[4:0] i s processor address bus. used to address internal registers within starlite tm . csn i s chip select. selects starlite tm as the source or destination of the current microprocessor bus cycle. csn needs only be active for one clock cycle to start a microprocessor access. dir i s direction. this signal indicates whether the access to the register specified by the pa bus is a read or a write. the polarity of this signal is programmed with the procmode0 pin. rdyn o a,s ready. indicates valid data is on the data bus during read operation and completion of write operation. its operation depends on procmode[1:0] settings. intrn o s interrupt. the compression and decompression processes generate interrupts that are reported with this signal. intrn is low whenever any non-masked bits are set in the interrupt status/control register. procmode[1:0] i s microprocessor port configuration mode. selects the polarity of the dir pin and operation of the csn pin. 00 active high write, fixed cycle 01 active low write, fixed cycle 10 active high write, variable cycle 11 active low write, variable cycle (see figure 2 through figure 5 for details.)
ps3410c-0600 page 25 of 47 advanced hardware architectures, inc. 5.2 data interface data interface signal type description d[31:0] i/o s data for all channels is transmitted on this bus. the ackn or fa[1:0] is used to distinguish between the four channels. data being written to starlite tm is latched on the rising edge of clock when the strobe condition is met. data setup and hold times are relative to clock. if the bus is configured to 16-bit transfers (wide=0), data is carried on d[15:0]. in this case, d[31:16] should be terminated with pullup resistors. driven i a drive enable. active low output driver enable. this input must be low in order to drive data onto d[31:0] in accordance with the current strobe condition. sd i s strobe delay. allows insertion of wait states for dma access to the fifos. the strobe condition, as programmed in the dsc field of system configuration 1 , enables this signal and selects its polarity. cireqn o s compression input data request, active low. this signal, when active, indicates the ability of the ci fifo to accept data. ciackn i s compression input data acknowledge for dma mode (dsc[3]=0). active low compression data input. this signal, when active, indicates the data on d is for the compression input fifo. data on d is latched on the rising edge of clock when the strobe condition is met. coreqn o a,s compression output data request, active low. when this signal is active, it indicates the ability of the co fifo to transmit data. coackn i s compression output data acknowledge for dma mode (dsc[3]=0). the definition of coackn varies with the data strobe condition in system configuration 1 . coeorn o s compression output end-of-record, active low. coeorn is active when the word currently on the output of the co fifo contains an end- of-record. direqn o s decompression input data request, active low. when this signal is active, it indicates the ability of the di port to accept data. diackn i s decompression input data acknowledge for dma mode (dsc[3]=0). active low decompression data input. when this signal is active, it indicates the data on d is for the decompression input port. data on d is latched on the rising edge of clock when the strobe condition is met. doreqn o a, s decompression output data request, active low. when this signal is active, it indicates the ability of the do port to transmit data. doackn i s decompression output data acknowledge for dma mode (dsc[3]=0). the definition of doackn varies with the data strobe condition in system configuration 1 .
page 26 of 47 ps3410c-0600 advanced hardware architectures, inc. 5.3 video interface 5.4 system control video interface signal type description vireqn o s video input request. active low output indicating that the vdi port is ready to accept another byte on vid[7:0]. viackn i s video input acknowledge. active low input indicating that vid[7:0] is being driven with a valid byte. vid[7:0] i s video input data. the value on this input bus is written into starlite tm when both vireqn and viackn are active. voreqn o s video output request. active low output indicating that the byte on vod[7:0] is valid. voackn i s video output acknowledge. active low input indicating that the external system is ready to read vod[7:0]. vod[7:0] o s video output data. the value on this output bus is read when both voreqn and voackn are low. voeorn o s video output end-of-record. active low output indicating that the byte on vod[7:0] contains the last byte in a record. system control signal type description clock i system clock. this signal is connected to the clock of the microprocessor. for amd microprocessors, this pin is either called memclk (29030 and 29200) or sysclk (29000). the intel i960cx calls this pin pclk. rstn i a power on reset. active low reset signal. starlite tm must be reset before any dma or microprocessor activity is attempted. rstn should be a minimum of 10 clock periods. test i a board test mode. when test is high, all outputs are tristated. when test is low, the chip performs normally.
ps3410c-0600 page 27 of 47 advanced hardware architectures, inc. 6.0 pinout pin designation signal pin signal pin signal pin signal pin vid[4] 1 d[7] 31 d[25] 61 vdd 91 vid[3] 2 d[8] 32 d[26] 62 vss 92 vid[2] 3 d[9] 33 d[27] 63 pa[4] 93 vid[1] 4 d[10] 34 d[28] 64 vdd 94 vid[0] 5 d[11] 35 d[29] 65 procmode[1] 95 intrn 6 vss 36 d[30] 66 procmode[0] 96 vss 7 vdd 37 vdd 67 csn 97 vdd 8 d[12] 38 vss 68 vdd 98 driven 9 d[13] 39 d[31] 69 vss 99 sd 10 d[14] 40 voreqn 70 dir 100 doackn 11 vss 41 voeorn 71 rstn 101 coackn 12 vss 42 vod[0] 72 pd[7] 102 diackn 13 vdd 43 vod[1] 73 pd[6] 103 ciackn 14 clk 44 vod[2] 74 pd[5] 104 vss 15 vss 45 vdd 75 vdd 105 vdd 16 vdd 46 vss 76 vss 106 doreqn 17 vss 47 vod[3] 77 pd[4] 107 coreqn 18 vdd 48 vod[4] 78 pd[3] 108 direqn 19 d[15] 49 vod[5] 79 pd[2] 109 cireqn 20 d[16] 50 vod[6] 80 pd[1] 110 vireqn 21 d[17] 51 vod[7] 81 pd[0] 111 d[0] 22 d[18] 52 coeorn 82 vdd 112 vss 23 d[19] 53 vdd 83 vss 113 vdd 24 d[20] 54 vss 84 rdyn 114 d[1] 25 d[21] 55 voackn 85 viackn 115 d[2] 26 d[22] 56 test 86 vid[7] 116 d[3] 27 d[23] 57 pa[0] 87 vid[6] 117 d[4] 28 d[24] 58 pa[1] 88 vid[5] 118 d[5] 29 vss 59 pa[2] 89 vdd 119 d[6] 30 vdd 60 pa[3] 90 vss 120
page 28 of 47 ps3410c-0600 advanced hardware architectures, inc. figure 16: pinout 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 vdd vss pa4 vdd procmode1 procmode0 csn vdd vss dir rstn pd7 pd6 pd5 vdd vss pd4 pd3 pd2 pd1 pd0 vdd vss rdyn viackn vid7 vid6 vid5 vdd vss vdd vss d24 d23 d22 d21 d20 d19 d18 d17 d16 d15 vdd vss vdd vss clk vdd vss vss d14 d13 d12 vdd vss d11 d10 d9 d8 d7 pa3 pa2 pa1 pa0 test voackn vss vdd coeorn vod7 vod6 vod5 vod4 vod3 vss vdd vod2 vod1 vod0 voeorn voreqn d31 vss vdd d30 d29 d28 d27 d26 d25 vid4 vid3 vid2 vid1 vid0 intrn vss vdd driven sd doackn coackn diackn ciackn vss vdd doreqn coreqn direqn cireqn vireqn d0 vss vdd d1 d2 d3 d4 d5 d6 aha3410c-025 pqc
ps3410c-0600 page 29 of 47 advanced hardware architectures, inc. 7.0 dc electrical specifications 7.1 operating conditions notes: 1) dynamic current (iout=0ma) - see figure 17 2) dynamic current; no data transfers 3) static current (clock high) 4) timings referenced to this load 5) output ac timings referenced to vol for high to low transitions and voh for low to high transitions. 7.2 absolute maximum stress ratings notes: 1) human body model operating conditions symbol parameter min max units notes vdd supply voltage 4.75 5.25 v idd supply current (active) 300 ma 1 idd supply current (standby) 26 ma 2 idd supply current (low power) 1 ma 3 ta ambient temperature 0 70 c vil input low voltage vss-0.5 0.8 v vih input high voltage 2.0 vdd+0.5 v ii input leakage current -10 10 a vol output low voltage (iol=-4ma) 0.4 v 5 voh output high voltage (ioh=4ma) 2.4 v 5 voh output high voltage (ioh=100 a) vdd-0.8 v 5 iol output low current 4 ma ioh output high current -4 ma ioz output leakage current -10 10 a ioz high impedance leakage current -10 10 a cin input capacitance 5 pf cout output capacitance 7 pf cio input/output capacitance 7 pf comax maximum capacitance load for all signals (including self loading) 50 pf 4 absolute maximum stress ratings symbol parameter min max units notes tstg storage temperature -50 150 c vdd supply voltage -0.5 7 v vin input voltage vss-0.5 vdd+0.5 v ilp latch-up current 100 ma esd electro-static discharge -2,000 +2,000 v 1
page 30 of 47 ps3410c-0600 advanced hardware architectures, inc. figure 17: power vs. data rate at 25 mhz operation notes: 1) power scales linearly with frequency at a given data rate. 2) iout=0 ma into 50 pf output loads. 400 300 200 100 10 15 20 25 idd (ma) rate (mb/s)
ps3410c-0600 page 31 of 47 advanced hardware architectures, inc. 8.0 ac electrical specifications figure 18: data interface timing table 6: data port timing requirements notes: 1) production test condition is 50 pf. delay is decreased 2 ns with 25 pf load guaranteed by design or characterization. 2) input timings are referenced to 1.4 volts. figure 19: request deasserts at eor, strobe condition of dsc=0-3, 6-15; erc=0 number parameter min max units notes 1 ciackn, diackn, coackn, doackn and sd setup time 8ns 2 ciackn, diackn, coackn, doackn and sd hold time 2ns2 3 d-bus input setup time 8 ns 4 d-bus input hold time 2 ns 5 reqn delay (non-eor case) 18 ns 1 6 reqn hold (non-eor case) 2 ns 7 d-bus, coeorn output delay 23 ns 8 d-bus, coeorn output hold 2 ns clock d reqn d, coeorn ackn, sd valid 0 valid valid 1 1 2 3 4 6 5 7 8 clock ackn reqn d sd eor-1 eor 1 2
page 32 of 47 ps3410c-0600 advanced hardware architectures, inc. figure 20: request deasserts at eor, strobe condition of dsc=0-3, 6-15; erc=1 figure 21: request deasserts at eor, strobe condition of dsc=4 or 5; erc=0 figure 22: request deasserts at eor, strobe condition of dsc=4 or 5; erc=1 clock ackn reqn d sd eor-1 eor 3 clock ackn reqn d sd eor-1 eor 4 clock ackn reqn d sd eor-1 eor 5
ps3410c-0600 page 33 of 47 advanced hardware architectures, inc. table 7: request vs. eor timing notes: 1) production test condition is 50 pf. delay is decreased 2 ns with 25 pf load guaranteed by design or characterization. figure 23: output enable timing table 8: output enable timing requirements number parameter min max units notes 1 ackn, sd to reqn dsc=0-15; erc=0 20 ns 1 2 clock to reqn dsc=0-3, 6-9; erc=0 21 ns 1 clock to reqn dsc=10-15; erc=0 23 ns 1 3 clock to reqn dsc=0-3, 6-15; erc=1 18 ns 1 4 clock to reqn dsc=4, 5; erc=0 21 ns 1 5 clock to reqn dsc=4, 5; erc=1 18 ns 1 number parameter min max units notes 1 driven to d valid 15 ns 2 driven to d tristate 10 ns 3 signal to d valid 15 ns 4 signal to d tristate 10 ns 5 clock to d tristate (dsc=100, 101) 15 ns clock ackn driven d 2 1 3 4 5
page 34 of 47 ps3410c-0600 advanced hardware architectures, inc. figure 24: video input port timing table 9: video input port timing requirements figure 25: video output port timing table 10: video output port timing requirements notes: 1) production test condition is 50 pf. delay is decreased 2 ns with 25 pf load guaranteed by design or characterization. number parameter min max units notes 1 vireqn delay 16 ns 2 vireqn hold 2 ns 3 viackn setup 8 ns 4 viackn hold 2 ns 5vid setup 8 ns 6 vid hold 2 ns number parameter min max units notes 1 voreqn delay 19 ns 1 2 voreqn hold 4 ns 3 voackn setup 8 ns 4 voackn hold 3 ns 5 vod delay 21 ns 1 6 vod hold 3.7 ns 7 voeorn hold 3.7 ns 8 voeorn delay 21 ns 1 clock viackn vid[7:0] vireqn 1 3 6 5 4 2 clock voackn vod[7:0] voreqn 1 2 4 3 6 voeorn 5 7 8
ps3410c-0600 page 35 of 47 advanced hardware architectures, inc. figure 26: microprocessor interface timing (procmode[1]=0) clock csn pa rdyn dir read 1 1 21 2 3 4 6 9 10 910 15 14 3 4 7 8 9 10 12 13 valid tristate valid tristate 910 valid pd dir pd write 234512
page 36 of 47 ps3410c-0600 advanced hardware architectures, inc. figure 27: microprocessor interface timing (procmode[1]=1) table 11: microprocessor interface timing requirements number parameter min max units notes 1 pa setup time 10 ns 2 pa hold time 3 ns 3 csn setup time 10 ns 4 csn hold time 3 ns 6 csn to valid rdyn 15 ns 7 rdyn valid delay 20 ns 8 rdyn drive disable 10 ns 9 dir setup time 10 ns 10 dir hold time 3 ns 12 pd valid delay 20 ns 13 pd drive disable 12 ns 14 pd setup time 10 ns 15 pd hold time 3 ns 16 csn high to pd tristate 10 ns 17 csn high to rdyn high 15 ns clock csn pa rdyn dir read 1 pd dir pd write 123 5n 4 valid valid a0 3 2 4 16 17 12 7 14 15 9 13 tristate 10
ps3410c-0600 page 37 of 47 advanced hardware architectures, inc. figure 28: interrupt timing table 12: interrupt timing requirements figure 29: clock timing table 13: clock timing requirements figure 30: power on reset timing table 14: power on reset timing requirements notes: 1) rstn signal can be asynchronous to the clock signal. it is internally synchronized to the rising edge of clock. number parameter min max units notes 1 intrn delay time 15 ns 2 intrn hold time 3 ns number parameter min max units notes 1 clock rise time 5 ns 2 clock fall time 5 ns 3 clock high time 15 ns 4 clock low time 16 ns 5 clock period 40 ns number parameter min max units notes 1 rstn low pulsewidth 10 clocks 2 rstn setup to clock rise 15 ns 1 3 rstn hold time 2 ns 1 clock intrn 1 2 clk 1 34 5 2 2.0v 1.4v 0.8v clock rstn 2 3 1
page 38 of 47 ps3410c-0600 advanced hardware architectures, inc. 9.0 package specifications package is jedec mo-108 l a a detail a a2 a1 e1 d1 p p d b e 117 118 119 120 30 29 28 27 26 aha3410c-025 pqc 91 92 93 94 (lca) (lcb)
ps3410c-0600 page 39 of 47 advanced hardware architectures, inc. jedec outline mo-108 10.0 ordering information 10.1 available parts 10.2 part numbering device number: 3410 revision letter: c package material codes: p plastic package type codes: q quad flat pack test specifications: c commercial 0 c to +70 c plastic quad flat pack package dimensions (all dimensions are in mm) symbol number of pin and specification dimension 120 sb min nom max (lca) 30 (lcb) 30 a 3.7 4.07 a1 0.25 0.33 a2 3.2 3.37 3.6 d 30.95 31.2 31.45 d1 27.99 28 28.12 e 30.95 31.2 31.45 e1 27.99 28 28.12 l 0.73 0.88 1.03 p0.8 b 0.3 0.35 0.4 part number description aha3410c-025 pqc 25 mbytes/sec simultaneous lossless data compression/ decompression coprocessor ic aha 3410 c- 025 p q c manufacturer device number revision level speed designation package material package type test specification
page 40 of 47 ps3410c-0600 advanced hardware architectures, inc. 11.0 related publications 11.1 aha technical publications * evaluation software is also available for unix operating system, upon request. 11.2 other technical publications document # description pb3410c aha product brief ? aha3410c starlite tm 25 mbytes/sec simultaneous lossless data compression/decompression coprocessor ic pb3411 aha product brief ? aha3411 starlite tm 33 mbytes/sec simultaneous compressor/decompressor ic pb3422 aha product brief ? aha3422 starlite tm 16 mbytes/sec lossless decompressor ic pb3431 aha product brief ? aha3431 starlite ? 40 mbytes/sec simultaneous compressor/decompressor ic, 3.3v ps3411 aha product specification ? aha3411 starlite tm 33 mbytes/sec simultaneous compressor/decompressor ic ps3422 aha product specification ? aha3422 starlite tm 16 mbytes/sec lossless decompressor ic ps3431 aha product specification ? aha3431 starlite tm 40 mbytes/sec simultaneous compressor/decompressor ic, 3.3v andc12 aha application note ? aha3410 starlite tm designer ? s guide andc13 aha application note ? compression performance on bitonal images andc14 aha application note ? starlite tm evaluation software andc15 aha application note ? encodeb2 compression algorithm description andc16 aha application note ? designer ? s guide for starlite tm family products: aha3411, aha3422 and aha3431 andc17 aha application note ? starlite tm compression on continuous tone images glgen1 general glossary of terms starsw starlite tm evaluation software (windows tm ) pctp127 t. summers, ? applying compression/decompression in high-performance printers and copiers ? , conference proceeding: the 1995 silicon valley personal computer design conference and exposition t. summers, ? compression technologies in printers ? , a paper presentation at seybold conference, 1995 document # description 7th edition, 1995 amd ? s fusion29k ? catalog 6th edition, 1995 intel ? s solutions 960 ? catalog 1996 edition motorola ? s 68k & coldfire ? source book: high performance embedded systems
ps3410c-0600 page 41 of 47 advanced hardware architectures, inc. appendix a: additional timing diagrams for dma mode transfers figure a1: dma mode timing for single word writes, strobe condition of dsc=000 figure a2: dma mode timing for single word reads, strobe condition of dsc=000 figure a3: dma mode timing for four word burst write, one wait state, strobe condition of dsc=000 clock ackn sd driven d d0 d1 clock ackn sd driven d d1 d0 clock ackn sd driven d d0 d2 d1 d3
page 42 of 47 ps3410c-0600 advanced hardware architectures, inc. figure a4: dma mode timing for four word burst read, one wait state, strobe condition of dsc=000 figure a5: dma mode timing for eight word burst write, zero wait state, strobe condition of dsc=000 figure a6: dma mode timing for eight word burst read, zero wait state, strobe condition of dsc=000 clock ackn sd driven d d1 d0 d2 d3 clock ackn sd driven d d0 d2 d1 d3 d4 d5 d6 d7 clock ackn sd driven d d0 d2 d1 d3 d4 d5 d6 d7
ps3410c-0600 page 43 of 47 advanced hardware architectures, inc. figure a7: dma mode timing for single word writes, strobe condition of dsc=010 figure a8: dma mode timing for single word reads, strobe condition of dsc=010 figure a9: dma mode timing for four word burst write, one wait state, strobe condition of dsc=010 clock ackn sd driven d d0 d1 clock ackn sd driven d d1 d0 clock ackn sd driven d d0 d2 d1 d3
page 44 of 47 ps3410c-0600 advanced hardware architectures, inc. figure a10: dma mode timing for four word burst read, one wait state, strobe condition of dsc=010 figure a11: dma mode timing for eight word burst write, zero wait state, strobe condition of dsc=010 figure a12: dma mode timing for eight word burst read, zero wait state, strobe condition of dsc=010 clock ackn sd driven d d1 d0 d2 d3 clock ackn sd driven d d0 d2 d1 d3 d4 d5 d6 d7 clock ackn sd driven d d2 d1 d3 d4 d5 d6 d7 d0
ps3410c-0600 page 45 of 47 advanced hardware architectures, inc. figure a13: dma mode timing for single word writes, strobe condition of dsc=011 figure a14: dma mode timing for single word reads, strobe condition of dsc=011 figure a15: dma mode timing for four word burst write, one wait state, strobe condition of dsc=011 clock ackn sd driven d d0 d1 clock ackn sd driven d d1 d0 clock ackn sd driven d d0 d2 d1 d3
page 46 of 47 ps3410c-0600 advanced hardware architectures, inc. figure a16: dma mode timing for four word burst read, one wait state, strobe condition of dsc=011 figure a17: dma mode timing for eight word burst write, zero wait state, strobe condition of dsc=011 figure a18: dma mode timing for eight word burst read, zero wait state, strobe condition of dsc=011 clock ackn sd driven d d1 d0 d2 d3 clock ackn sd driven d d0 d2 d1 d3 d4 d5 d6 d7 clock ackn sd driven d d2 d1 d3 d4 d5 d6 d7 d0
ps3410c-0600 page 47 of 47 advanced hardware architectures, inc. figure a19: dma mode timing for single word writes, strobe condition of dsc=111 figure a20: dma mode timing for single word reads, strobe condition of dsc=111 clock ackn sd driven d d0 d1 d2 clock ackn sd driven d d1 d0 d2

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